HyperBus Memory Controller IP Package

HyperBus Memory Controller IP Package


The IP Package is a collection of RTL (Register-transfer level) source code and documentation intended to help designers add support for HyperBus to their FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), or ASSP (Application-Specific Standard Product) host controller platform. The Controller IP supports both HyperFlash™ and HyperRAM™ products.

The HyperBus Master Interface Controller IP Package includes the following software and materials:

  • HyperBus Controller Verilog HDL RTL Source Code
  • HyperBus Controller IP SpecificationIntroduction to future steering concept for automated trucks
  • System Verilog Test Bench (AXI4 and AXI3)
  • Verilog Memory Behavioral Model (HyperFlash and HyperRAM)
  • Test Specification
  • Test (Verification Report)
  • Test Script
  • Application Note for AMBA AXI
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