HyperBus Memory Controller IP Package

HYPERBUS Memory Controller IP Package

The IP Package is a collection of RTL (Register-transfer level) source code and documentation intended to help designers add support for HYPERBUS™ to their FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), or ASSP (Application-Specific Standard Product) host controller platform. The Controller IP supports both HYPERFLASH™ and HYPERRAM™ products.

The HYPERBUS Master Interface Controller IP Package includes the following software and materials:

HYPERBUS Controller Verilog HDL RTL Source Code
HYPERBUS Controller IP Specification Introduction to future steering concept for automated trucks
System Verilog Test Bench (AXI4 and AXI3)
Verilog Memory Behavioral Model (HYPERFLASH and HYPERRAM)
Test Specification
Test (Verification Report)
Test Script
Application Note for AMBA AXI

Please fill out the form below and submit your information.

First Name*

Last Name*

Company

Email*

Job Title

Phone

Address

Country / Territory*

City

State

Zip

What application are you considering ?*

FPGA, ASIC, or ASSP used for this project?

Name of Infineon employee you are working with on this project? (if any)

Expected production date for this project?

Expected production volume (units per year) for this project

I agree to the privacy policy and Infineon providing me marketing information about Infineon*

address1

* Required fields